1. Field of the Invention
The present invention relates to a circuit configuration of an internal input/output (I/O) buffer which permits a timing verification test of high accuracy for semiconductor devices (hereinafter referred to as "LSI" in some cases).
2. Description of the Background Art
FIG. 19 shows a conventional configuration in which a test of an LSI is carried out with a semiconductor testing apparatus (hereinafter referred to as "LSI tester" in some cases).
An LSI tester 500 comprises a tester body 504 and a test head 506. The tester body 504 has a timing generator 501 for generating timing signals needed as LSI test conditions, a waveform formatter 502 for determining waveforms of the rise and fall timings and the like, and a power supply and DC measuring unit 503 comprising a power supply for driving a device and a section for measuring DC of a device. The test head 506 performs direct giving and receiving of signals between an LSI under test 505, based on a control signal obtained through a cable 507 from the tester body 504.
When conducting a test of the LSI under test 505, a test signal is generated from a tester driver 509 of pin electronics which is housed in the test head 506, and the test signal is applied to the LSI under test 505 through POGO pins 510, a wire 512 of a DUT board 511, an electrode 514 of a socket 513, and a wire 516 of an LSI package 515. Conversely, the reaction signal obtained after the LSI 505 operates is transferred to a tester comparator 517 of the LSI tester 500 through a similar path. The tester comparator 517 then compares the reaction signal with an expected value EXP, so that the LSI tester 500 judges whether or not the LSI 505 is operating in conformity with design.
Where the LSI 505 is tested with the LSI tester 500 as described, the following problems have caused in conducting one of test items, a timing verification test. With increasing the operation speed of the LSI 505, the interface of the LSI 505 is required to operate in a clock of several hundreds MHz grade, and thus the product specification of the LSI 505, e.g., the setup and hold timing value, becomes extremely small, which causes difficulties in carrying out an accurate timing verification test with the LSI tester 500 under severe timing conditions.
One concrete example will be described with reference to FIGS. 20 and 21. FIG. 20 shows the configuration of a conventional I/O buffer cell 520. FIG. 21 shows a timing relationship between a data terminal 521 and a clock terminal 522 when a timing verification test is conducted.
Referring to FIG. 20, a clock CLK obtained from the clock terminal 522 is provided to the control inputs of a driver 524 and a receiver 525 through a clock input section 611. The operations of the driver 524 and the receiver 525 are controlled by the clock CLK.
Data DATA obtained from the data terminal 521 is provided to a first input of the receiver 525 through a data I/O section 612, and a reference voltage V.sub.REF is provided to a second input of the receiver 525 through a reference voltage input section 607. The receiver 525 compares the data DATA and the reference voltage V.sub.REF and outputs an internal signal which is obtained by buffering based on its comparison result, to an internal logic 523 through a signal output section 610.
The output from the internal logic 523 is taken as the input to the driver 524, through a signal input section 609. The output of the driver 525 is outputted to the data terminal 521 through the data I/O section 612.
For example, assuming that the product standard of the setup timing of data DATA against the clock CLK of the I/O buffer cell 520 mounted on the LSI under test 505, is 0.2 ns, it will be discussed the case where a timing verification test of whether the I/O buffer cell 520 in the LSI 505 satisfies the timing condition, i.e., the setup time of 0.2 ns, is carried out with the LSI tester 500.
Even where a timing verification test at a setup TS0 is conducted when the waveform of data DATA is L1 and that of a clock CLK is L3 in FIG. 21, the fact is that a skew .alpha. a causes in both the data DATA and clock CLK Therefore, if the phase of the data DATA is advanced like waveform L2, and the phase of the clock CLK is delayed like waveform L4, the timing verification test might be conducted at a setup time TS2 significantly greater than a preset setup time TS1.
Specifically, provided that a variation in signal propagation time due to a timing skew of signals generated by the LSI tester 500 is .+-.0.15 ns, a variation in signal propagation time due to the lengths of the wire 512 of the DUT board 511 and the electrode 514 of the socket 513 is .+-.0.05 ns, and a variation in signal propagation time due to the length of the wire 516 of the package 515 is .+-.0.1 ns, the maximum phase difference in signal between the clock CLK and the data DATA is 0.6 ns.
Accordingly, even when the clock CLK has a phase lag of 0.6 ns as compared to the data DATA, a test program value should be set to -0.4 ns (the phase of the clock CLK is 0.4 ns ahead the data DATA) in order to positively assure the setup of the product standard, i.e., 0.2 ns. This is because when a test program value tp is set to a value greater than -0.4 ns, if the clock CLK has a phase lag of 0.6 ns as compared to the data DATA, a timing verification test might be conducted at a setup time greater than 0.2 (tp+0.6), thereby causing the danger that the LSI under test 505 not satisfying the setup time of 0.2 ns is erroneously judged good.
Even though the test program value tp is set to -0.4 ns, however, there is the possibility that since a timing skew in the LSI tester 500 still exists, it results in -1.0 ns when the worst happens in an actual timing applied to the LSI 505 (i.e., the case where the data DATA has a phase lag of 0.6 ns as compared to the clock CLK).
When the above worst timing is applied to the LSI 505, the great majority of the LSI 505 are judged poor, originally to be judged good. This leads to excessive drop in the yield of the LSI 505.